Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device with buried bit lines.
High-integration Dynamic Random Access Memory (DRAM) devices manufactured using under 50 nm process are being developed. Accordingly, a cell structure of 8F2, where F denotes a minimum feature size, has been transitioning to a cell structure of 6F2 to increase a net die through the improvement in the integration degree. Moreover, a more highly integrated cell structure of 4F2 has been also being developed intensively. In the cell structure of 4F2, vertical gates (VG) are introduced. With the vertical gates, cells come to have vertical channel transistors. The vertical channel transistors are transistors where a vertical gate (or word line) is formed on the sidewalls of each pillar and thus a channel is formed in a vertical direction. Along with the introduction of the vertical channel transistors, buried bit lines (BBL) are formed to intensify the integration degree of cells. The buried bit lines are formed through an ion implantation of a dopant.
However, when the sizes of semiconductor devices shrink, decreasing the resistance of the buried bit lines by using an ion-implantation technique are reaching limits.
Here, since various processes are performed after the formation of buried bit lines, the surface of the buried bit lines may be damaged.